外文翻译-VHDL语言介绍.doc
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1、英文原文原文出处:DOUGLASLP.VHDL:programming by exampleMNew York:McGrawHill Professional2002FOREWORDVHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. For almost 15 years the electronic design automation industry has expanded the use of VHDL from init
2、ial concept of design documentation, to design implementation and func tional verification. It can be said that VHDL fueled modern synthesis technology and enabled the development of ASIC semiconductor compa nies. This book has served as the authoritative source of practical information on the use o
3、f VHDL for users of the language around the world.The use of VHDL has evolved and its importance increased as semi conductor devices dimensions have shrunk. Not more than 10 years ago it was common to mix designs described with schematics and VHDL. But as design complexity grew, the industry abandon
4、ed schematics in favor of the hardware description language only. The successive revisions of this book have always kept pace with the industrys evolving use of VHDL.The fact that VHDL is adaptable is a tribute to its architecture. The industry has seen the use of VHDLs package structure to allow de
5、sign ers, electronic design automation companies and the semiconductor indus try to experiment with new language concepts to ensure good design tool and data interoperability. When the associated data types found in the IEEE 1164 standard were ratified, it meant that design data interoper ability wa
6、s possible.All of this was facilitated by industry backing in a consortium of systems, electronic design automation and semiconductor companies now known as Accellera.And when the ASIC industry needed a standard way to convey gate-level design data and timing information in VHDL, one of Accelleras p
7、rogenitors (VHDL International) sponsored the IEEE VHDL team to build a companion standard. The IEEE 1076.4 VITAL (VHDL Initiative Towards ASIC Libraries) was created and ratified as offers designers a single language flow from concept to gate-level signoff.In the late 90s, the Verilog HDL and VHDL
8、industry standards teams collaborated on the use of a common timing data such as IEEE 1497 SDF, set register transfer level (RTL) standards and more to improve design methodologies and the external connections provided to the hardware description languages.But from the beginning, the leadership of t
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